The present invention relates to a semiconductor device, and more particularly, to a semiconductor device that secures a data valid window of a data output in synchronization with a clock signal, and an operation method of the semiconductor device.
A semiconductor device such as a double data rate synchronous DRAM (DDR SDRAM) receives an external clock signal to generate an internal clock signal. Between the external clock signal and the internal clock signal, clock skew may occur due to delay in the semiconductor device. Accordingly, the semiconductor device includes a clock synchronization circuit for compensating it, such as a phase locked loop (PLL) and a delay locked loop (DLL).
This internal clock signal is input into various circuits in the semiconductor device to serve as a reference.
FIG. 1 is a circuit diagram of a typical semiconductor device.
Referring to FIG. 1, the typical semiconductor device includes a DLL 110, a pulse generator 130, a pre-driver 150 and a main driver 170.
The DLL 110 compensates clock skew of an external clock signal CLK_EXT to generate a rising DLL clock signal RCLK_DLL and a falling DLL clock signal FCLK_DLL. The rising DLL clock signal RCLK_DLL corresponds to a rising edge of the external clock CLK_EXT, and the falling DLL clock signal FCLK_DLL corresponds to a falling edge of the external clock CLK_EXT.
The pulse generator 130 receives the rising DLL clock signal RCLK_DLL and the falling DLL clock signal FCLK_DLL to output a first drive control signal CTR_PDR1 and a second drive control signal CTR_PDR2 as pulse signals. In more detail, the pulse generator 130 includes a first pulse generator 132 and a second pulse generator 134. The first pulse generator 132 controls a pulse width of the rising DLL clock signal RCLK_DLL to generate the first drive control signal CTR_PDR1. The second pulse generator 134 controls a pulse width of the falling DLL clock signal FCLK_DLL to generate the second drive control signal CTR_PDR2.
The pre-driver 150 receives a first data DAT1 in response to the first drive control signal CTR_PDR1 and a second data DAT2 in response to the second control signal CTR_PDR2 to latch and output them. The main driver 170 drives an output terminal DQ in response to the first and second data DAT1 and DAT2 received from the pre-driver 150.
In more detail, the pre-driver 150 includes a first pre-driver 152 and a second pre-driver 154. Each of the first and second pre-drivers 152 and 154 receives the first data DAT1 in response to the first drive control signal CTR_PDR1 and the second data DAT2 in response to the second drive control signal CTR_PDR2 to latch and output them. The main driver 170 includes a pull-up driver 172 and a pull-down driver 174. The pull-up driver 172 pulls up the output terminal DQ in response to an output signal of the first pre-driver 172. The pull-down driver 174 pulls down the output terminal DQ in response to an output signal of the second pre-driver 174.
A simple exemplary operation of the typical semiconductor device of FIG. 1 will be described below. The DLL 110 generates the rising DLL clock signal RCLK_DLL and the falling DLL clock signal FCLK_DLL. The first pulse generator 132 receives the rising DLL clock signal RCLK_DLL to generate the first drive control signal CTR_PDR1, and the second pulse generator 134 receives the falling DLL clock signal FCLK_DLL to generate the second drive control signal CTR_PDR2. Here, the first and second pulse generators 132 and 134 control pulse widths of the first drive control signal CTR_PDR1 and the second drive control signal CTR_PDR2, respectively. As such, it is possible to prevent overlapping of activation periods of the first and second drive control signals CTR_PDR1 and CTR_PDR2.
Accordingly, interference of the first and second data DAT1 and DAT2 can also be prevented while they are input to each of the first and second pre-drivers 152 and 154 in response to the first and second drive control signals CTR_PDR1 and CTR_PDR2.
The main driver 170 pulls up or down the output terminal DQ in response to the first data DAT1 received from the first and second pre-drivers 152 and 154. Thereafter, the main drier 170 pulls up or down the output terminal DQ in response to the second data DAT2 input from the first and second pre-drivers 152 and 154.
However, as operation frequency of a semiconductor device increases, the first and second clock generators 132 and 134 may operate abnormally. Consequently, the activation periods of the first and second drive control signals CTR_PDR1 and CTR_PDR2 may overlap each other. This may be caused by variations of process, voltage and temperature (PVT), distortions of the rising and falling DLL clock signals RCLK_DLL and FCLK_DLL, and loading difference between transfer lines of the rising DLL clock signal RCLK_DLL and the falling DLL clock signal FCLK_DLL.
In the case where the activation periods of the first drive control signal CTR_PDR1 and the second drive control signal CTR_PDR2 overlap each other, a first transfer gate TG1 and a second transfer gate TG2 of the first pre-driver 152 may turn on simultaneously. Therefore, the first and second data DAT1 and DAT2 may input to the first pre-driver 152 simultaneously, which may result in interference of the first and second data DAT1 and DAT2. This is the same in the case of the second pre-driver 154.
If the first and second data DAT1 and DAT2 have different logic levels from each other, for example, if the first data DAT1 has a logic high level and the second data DAT2 has a logic low level, in a duration where the activation periods of the first and second drive control signals CTR_PDR1 and CTR_PDR2 overlap each other, the first and second data DAT1 and DAT2 interfere with each other. Then, the main driver 170 cannot secure stable operation timings for a pull-up operation and a pull-down operation.
Consequently, a data valid window of data output from the output terminal DQ may become irregular, and thus duty ratio may be distorted. This means that the semiconductor device cannot output data of a stable voltage level at a desired timing. In addition, interference of the first and second data DAT1 and DAT2 may generate an unwanted current path, thereby increasing unnecessary current consumption.